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integrated circuit systems, inc. ics951403 0486b?02/23/04 block diagram functionality pin configuration 48-pin ssop & tssop recommended application: ati chipset with k7 systems output features: 3 differential pair open drain cpu clocks (1.5v external pull-up; up to 150mhz achieviable through i 2 c) 2 - agpclk @ 3.3v 8 - pci @3.3v, including 1 free running 1 - 48mhz @ 3.3v 1 - 24/48mhz @ 3.3v 2- ref @3.3v, 14.318mhz. features: programmable ouput frequency programmable ouput rise/fall time programmable group skew real time system reset output spread spectrum for emi control typically by 7db to 8db, with programmable spread percentage watchdog timer technology to reset system if over-clocking causes malfunction uses external 14.318mhz crystal asyncronous cpu and sdram clocks cpu and pci outputs are aligned cpu - agp skew <500ps amd-k7 tm system clock chip * internal 120k pullup resistor on indicated inputs ** internal 240k pullup resistor on indicated inputs power groups vdd48, gnd48 = 48mhz, pll2 vddref, gndref= ref, x1, x2 vdd, gnd = pll core sel24_48# s data sclk fs (2:0) pd# pci_stop# cpu_stop# spread# pll2 pll1 spread spectrum 48mhz 24_48mhz sdram_out pciclk (6:0) agp (1:0) pciclk_f 2 7 x1 x2 xtal osc cpu divder sdram divder pci divder agp divder stop stop control logic config. reg. / 2 ref (1:0) 3 3 cpuclkt (2:0) cpuclkc (2:0) 0 0 0 0 100.00 100.00 33.33 66.67 50.00 0 0 0 1 100.00 133.33 33.33 66.67 50.00 0 0 1 0 100.00 150.00 30.00 60.00 50.00 0 0 1 1 100.00 66.67 33.33 66.67 50.00 0 1 0 0 133.33 133.33 33.33 66.67 50.00 0 1 0 1 125.00 100.00 31.25 62.50 50.00 0 1 1 0 124.00 124.00 31.00 62.00 46.50 0 1 1 1 133.33 100.00 33.33 66.67 50.00 1 0 0 0 112.00 112.00 33.60 67.20 56.00 1 0 0 1 150.00 150.00 30.00 60.00 50.00 1 0 1 0 111.11 166.67 33.33 66.67 55.56 1 0 1 1 110.00 165.00 33.00 66.00 55.00 1 1 0 0 166.67 166.67 33.33 66.67 55.56 1 1 0 1 90.00 90.00 30.00 60.00 45.00 1 1 1 0 48.00 48.00 32.00 64.00 48.00 1 1 1 1 45.00 60.00 30.00 60.00 45.00 pciclk bit 7 fs2 fs1 fs0 cpu sdram agp sel = 0 agp sel = 1
2 ics951403 0486b?02/23/04 pin descriptions r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 1 , 2 ) 0 : 1 ( s fn id d v o t p u - l l u p s a h , s n i p t c e l e s y c n e u q e r f ) 0 : 1 ( f e rt u ot u p t u o k c o l c z h m 8 1 3 . 4 1 , 5 2 , 1 2 , 6 , 3 7 4 , 1 4 , 8 3 , 3 3 d n gr w pd n u o r g 41 xn i f p 3 3 l a n r e t n i s a h , t u p n i l a t s y r c z h m 8 1 3 . 4 1 n i _ l a t x 2 x m o r f r o t s i s e r k c a b d e e f d n a p a c d a o l 52 xt u of p 3 3 p a c d a o l l a n r e t n i s a h , t u p t u o l a t s y r c t u o _ l a t x 7f _ k l c i c pt u o e h t y b d e t c e f f a t o n . t u p t u o i c p g n i n n u r e e r f . t u p n i # p o t s _ i c p , 0 1 , 1 1 , 3 1 , 4 1 , 6 1 , 7 1 8 ) 0 : 6 ( k l c i c pt u ov 3 . 3 e l b i t a p m o c l t t . s t u p t u o k c o l c i c p 5 1 , 9i c p d d vr w pv 3 . 3 y l l a n i m o n , s t u p t u o k l c i c p r o f r e w o p 8 1p g a d d vr w pv 3 . 3 y l l a n i m o n , s t u p t u o p g a r o f r e w o p 9 1 , 0 2) 0 : 1 ( p g at u o e b t o n y a m e s e h t . i c p x 2 s a d e n i f e d s t u p t u o p g a . d e p p o t s 4 3d d vr w pv 3 . 3 y l l a n i m o n , e r o c r o f r e w o p d e t a l o s i 2 28 4 d d vr w pv 3 . 3 y l l a n i m o n s t u p t u o z h m 4 2 d n a z h m 8 4 r o f r e w o p 3 2z h m 8 4t u ot u p t u o z h m 8 4 4 2 # 8 4 - 4 2 l e sn i 4 2 n i p r o f t u p t u o z h m 8 4 r o 4 2 s t c e l e s z h m 4 2 = h g i h z h m 8 4 = w o l z h m 8 4 - 4 2t u o# 8 4 - 4 2 l e s h g u o r h t e l b a t c e l e s t u o k c o l c d e x i f 6 2k l c sn ii f o n i p k c o l c 2 t n a r e l o t v 5 y r t i u c r i c c 7 2a t a d so / ii r o f n i p a t a d 2 t n a r e l o t v 5 y r t i u c r i c c 8 22 s fn id d v o t p u - l l u p s a h , n i p t c e l e s y c n e u q e r f 9 2# d a e r p sn i n w o d . w o l n e h w e r u t a e f m u r t c e p s d a e r p s s e l b a n e z h k 0 5 = y c n e u q e r f n o i t a l u d o m % 5 . 0 d a e r p s 0 3# d pn i s t u p t u o l l a & l l p l a n r e t n i . w o l e v i t c a , p i h c n w o d s r e w o p . d e l b a s i d e r a 1 3# p o t s _ u p cn i s a r e h w w o l n e v i r d s i t k l c u p c . s k l c u p c s t l a h d e t r e s s a s i n i p s i h t n e h w h g i h n e v i r d s i c k l c u p c . ) w o l e v i t c a ( 2 3# p o t s _ i c pn i . w o l n e v i r d n e h w l e v e l " 0 " c i g o l t a s u b i c p s t l a h n i p s i h t y b d e t c e f f a t o n s i f _ k l c i c p 5 3 # t e s e rt u o r e m t g o d h c t a w r o f l a n g i s t e s e r m e t s y s e m i t l a e r . w o l e v i t c a s i l a n g i s s i h t . t u o e m i t 6 4t u o _ m a r d st u or e f f u b y a l e d o r e z m a r d s r o f k c o l c e c n e r e f e r 4 4d e v r e s e rc / nl i a r r e w o p u p c e r u t u f 6 3 , 9 3 , 2 4) 0 : 2 ( t k l c u p ct u o n e p o e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " e u r t " . p u - l l u p v 5 . 1 l a n r e t x e n a d e e n s t u p t u o n i a r d 7 3 , 0 4 , 3 4) 0 : 2 ( c k l c u p ct u o . t u p t u o u p c r i a p l a t n e r e f f i d f o s k c o l c " y r a t n e m e l p m o c " . p u _ l l u p v 5 . 1 l a n r e t x e n a d e e n s t u p t u o n i a r d n e p o e s e h t 5 4d s d d vr w pv 3 . 3 y l l a n i m r o n . n i p t u o _ m a r d s r o f r e w o p 8 4f e r d d vr w pv 3 . 3 y l l a n i m o n , 2 x , 1 x , f e r r o f r e w o p general description the ics951403 is a main clock synthesizer chip for amd-k7 based systems with ati chipset. this provides all clocks required for such a system. the ics951403 belongs to ics new generation of programmable system clock generators. it employs serial programming i 2 c interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/ enabling individual clocks. this device also has ics propriety 'watchdog timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking.
3 ics951403 0486b?02/23/04 note: pwd = power-up default note1: default at power-up will be for latched logic inputs to define frequency, as displayed by bit 3. t i bn o i t p i r c s e dd w p 2 t i b 4 : 7 t i b 2 t i b7 t i b 6 t i b5 t i b4 t i b u p cm a r d si c p p g a 0 = l e s p g a 1 = l e s e g a t n e c e r p d a e r p s - 0 0 0 0 0 1 e t o n 2 s f1 s f0 s f 000 0 0 0 0 . 0 0 10 0 . 0 0 13 3 . 3 37 6 . 6 60 0 . 0 5d a e r p s n w o d % 5 . 0 - o t 0 000 0 1 0 0 . 0 0 13 3 . 3 3 13 3 . 3 37 6 . 6 60 0 . 0 5d a e r p s n w o d % 5 . 0 - o t 0 000 1 0 0 0 . 0 0 10 0 . 0 5 10 0 . 0 30 0 . 0 60 0 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 000 1 1 0 0 . 0 0 17 6 . 6 63 3 . 3 37 6 . 6 60 0 . 0 5d a e r p s n w o d % 5 . 0 - o t 0 00 10 0 3 3 . 3 3 13 3 . 3 3 13 3 . 3 37 6 . 7 60 0 . 0 5d a e r p s n w o d % 5 . 0 - o t 0 00 10 1 0 0 . 5 2 10 0 . 0 0 15 2 . 1 30 5 . 2 60 0 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 00 1 1 0 0 0 . 4 2 10 0 . 4 2 10 0 . 1 30 0 . 2 60 5 . 6 4d a e r p s r e t n e c % 5 2 . 0 - / + 00 1 1 1 3 3 . 3 3 10 0 . 0 0 13 3 . 3 37 6 . 6 60 0 . 0 5d a e r p s n w o d % 5 . 0 - o t 0 0100 0 0 0 . 2 1 10 0 . 2 1 10 6 . 3 30 2 . 7 60 0 . 6 5d a e r p s r e t n e c % 5 2 . 0 - / + 0100 1 0 0 . 0 5 10 0 . 0 5 10 0 . 0 30 0 . 0 60 0 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 010 10 1 1 . 1 1 17 6 . 6 6 13 3 . 3 37 6 . 6 66 5 . 5 5d a e r p s r e t n e c % 5 2 . 0 - / + 010 1 1 0 0 . 0 1 10 0 . 5 6 10 0 . 3 30 0 . 6 60 0 . 5 5d a e r p s r e t n e c % 5 2 . 0 - / + 0110 0 7 6 . 6 6 17 6 . 6 6 13 3 . 3 37 6 . 6 66 5 . 5 5d a e r p s r e t n e c % 5 2 . 0 - / + 0110 1 0 0 . 0 90 0 . 0 90 0 . 0 30 0 . 0 60 0 . 5 4d a e r p s r e t n e c % 5 2 . 0 - / + 01110 0 0 . 8 40 0 . 8 40 0 . 2 30 0 . 4 60 0 . 8 4d a e r p s r e t n e c % 5 2 . 0 - / + 0111 1 0 0 . 5 40 0 . 0 60 0 . 0 30 0 . 0 60 0 . 5 4d a e r p s r e t n e c % 5 2 . 0 - / + 10 0 0 0 0 3 . 0 0 10 3 . 0 0 13 4 . 3 37 8 . 6 65 1 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 10 0 0 1 0 3 . 0 0 13 7 . 3 3 13 4 . 3 37 8 . 6 65 1 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 10 0 1 0 0 0 . 5 0 10 5 . 7 5 10 5 . 1 30 0 . 3 60 5 . 2 5d a e r p s r e t n e c % 5 2 . 0 - / + 10 0 1 1 0 3 . 0 0 17 8 . 6 63 4 . 3 37 8 . 6 65 1 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 10 1 0 0 0 0 . 0 1 10 0 . 0 1 10 0 . 3 30 0 . 6 60 0 . 5 5d a e r p s r e t n e c % 5 2 . 0 - / + 10 1 0 1 0 0 . 3 0 10 0 . 3 0 13 3 . 4 37 6 . 8 60 5 . 1 5d a e r p s r e t n e c % 5 2 . 0 - / + 10 1 1 0 0 0 . 3 0 13 3 . 7 3 13 3 . 4 37 6 . 8 60 5 . 1 5d a e r p s r e t n e c % 5 2 . 0 - / + 10 1 1 1 3 7 . 3 3 10 3 . 0 0 13 4 . 3 37 8 . 6 65 1 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 110 0 0 3 7 . 3 3 13 7 . 3 3 13 4 . 3 37 8 . 6 65 1 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 110 0 1 0 0 . 0 4 10 0 . 0 4 10 0 . 5 30 0 . 0 70 5 . 2 5d a e r p s r e t n e c % 5 2 . 0 - / + 110 1 0 3 3 . 7 3 10 0 . 3 0 13 3 . 4 37 6 . 8 60 5 . 1 5d a e r p s r e t n e c % 5 2 . 0 - / + 110 1 1 3 3 . 7 3 13 3 . 7 3 13 3 . 4 37 6 . 8 60 5 . 1 5d a e r p s r e t n e c % 5 2 . 0 - / + 1110 0 0 0 . 5 0 10 0 . 5 0 10 0 . 5 30 0 . 0 70 5 . 2 5d a e r p s r e t n e c % 5 2 . 0 - / + 1110 1 3 3 . 8 3 13 3 . 8 3 18 5 . 4 37 1 . 9 68 8 . 1 5d a e r p s r e t n e c % 5 2 . 0 - / + 111 1 0 0 0 . 0 0 20 0 . 0 0 23 3 . 3 37 6 . 6 60 0 . 0 5d a e r p s r e t n e c % 5 2 . 0 - / + 111 1 1 5 2 . 4 0 10 0 . 9 3 15 7 . 4 30 5 . 9 63 1 . 2 5d a e r p s r e t n e c % 5 2 . 0 - / + 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 7 2 , t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 d e l b a n e m u r t c e p s d a e r p s - 1 0 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0
4 ics951403 0486b?02/23/04 byte 1: output control register (1= enable, 0 = disable) byte 2: pci stop register (1= enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. 2. latched frequency selects (fs#) will be inverted logic load of the input frequency select pin conditions. byte 4: 24/48mhz control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7-x d e v r e s e r 6x k c a b - d a e r 2 s f 5x k c a b - d a e r 1 s f 4x k c a b - d a e r 0 s f 311 1 f e r 221 0 f e r 10 21 1 p g a 09 11 0 p g a byte 5: clock enable control register (1= enable, 0 = disable) byte 3: cpu free running control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b71 f _ k l c i c p 6 t i b7 11 6 k l c i c p 5 t i b6 11 5 k l c i c p 4 t i b4 11 4 k l c i c p 3 t i b3 11 3 k l c i c p 2 t i b1 11 2 k l c i c p 1 t i b0 11 1 k l c i c p 0 t i b81 0 k l c i c p t i b# n i pd w pn o i t p i r c s e d 7 t i b-x d e v r e s e r 6 t i b-x d e v r e s e r 5 t i b-x d e v r e s e r 4 t i b-x d e v r e s e r 3 t i b-0 d e v r e s e r 2 t i b-0 0 c / t u p c 1 t i b-0 1 c / t u p c 0 t i b-0 2 c / t u p c t i b# n i pd w pn o i t p i r c s e d 7 t i b4 21 8 4 / 4 2 l e s z h m 8 4 = 1 z h m 4 2 = 0 6 t i b7 31 0 c k l c u p c 5 t i b6 31 0 t k l c u p c 4 t i b0 41 1 c k l c u p c 3 t i b9 31 1 t k l c u p c 2 t i b3 41 2 c k l c u p c 1 t i b2 41 2 t k l c u p c 0 t i b6 41 t u o _ m a r d s byte 6: control register (1= enable, 0 = disable) notes: 3. bytes 7:14 not defined. t i b# n i pd w pn o i t p i r c s e d 7-1 d e v r e s e r 64 21 z h m 8 4 - 4 2 5-1 z h m 8 4 4-1 d e v r e s e r 3-1 d e v r e s e r 2-1 d e v r e s e r 1-0 t c e l e s y c n e u q e r f p g a z h m 0 . 0 5 = 1 z h m 6 . 6 6 = 0 0-1 d e v r e s e r t i b# n i pd w pn o i t p i r c s e d 7-0 x 2 = 1 x 1 = 0 h t g n e r t s f e r 6-0 p o t s 2 : 1 t , 2 : 1 c u p c = 0 g n i n n u r e e r f 2 : 1 t , 2 : 1 c u p c = 1 5-0 d e v r e s e r 4-x k c a b - d a e r # d a e r p s 3-x k c a b - d a e r # p o t s _ u p c 2-x k c a b - d a e r # p o t s _ i c p 1-x d e v r e s e r 0-0 e l g g o t d e e p s p g a
5 ics951403 0486b?02/23/04 byte 15: cpu_sdram skew register byte 16: slew rate control register notes: 1. pwd = power on default t i bd w pn o i t p i r c s e d 7 t i b -d e v r e s e r 6 t i b -d e v r e s e r 5 t i b -d e v r e s e r 4 t i b -d e v r e s e r 3 t i b -d e v r e s e r 2 t i b -d e v r e s e r 1 t i b -d e v r e s e r 0 t i b -d e v r e s e r t i bd w pn o i t p i r c s e d 7 t i b 1 ) d e n n a c l e d p ( m a r d s 6 t i b 0 5 t i b 0 d e v r e s e r 4 t i b 1 3 t i b 1 ) d e n n a c l e d p ( 0 t & 0 c u p c 2 t i b 1 1 t i b 1 ) d e n n a c l e d p ( 2 : 1 t & 2 : 1 c u p c 0 t i b 0 byte 19: slew rate control register byte 20: slew rate control register t i bd w pn o i t p i r c s e d 7 t i b 1 l o r t n o c w e l s ) 0 : 3 ( i c p 6 t i b 0 5 t i b 1 l o r t n o c w e l s f _ i c p 4 t i b 0 3 t i b 1 l o r t n o c w e l s 0 c k l c u p c 2 t i b 0 1 t i b 1 l o r t n o c w e l s 0 t k l c u p c 0 t i b 0 byte 17: slew rate control register byte 18: slew rate control register t i bd w pn o i t p i r c s e d 7 t i b 1 l o r t n o c w e l s ) 7 : 4 ( i c p 6 t i b 0 5 t i b 1 l o r t n o c w e l s 1 p g a 4 t i b 0 3 t i b 1 l o r t n o c w e l s 0 p g a 2 t i b 0 1 t i b 1 d e v r e s e r 0 t i b 0 t i bd w pn o i t p i r c s e d 7 t i b 1 l o r t n o c w e l s z h m 8 4 6 t i b 0 5 t i b 1 l o r t n o c w e l s z h m 8 4 , 4 2 4 t i b 0 3 t i b 1l o r t n o c w e l s 0 f e r 2 t i b 0l o r t n o c w e l s 1 f e r 1 t i b 1 l o r t n o c w e l s m a r d s 0 t i b 0 t i bd w pn o i t p i r c s e d 7 t i b 1 l o r t n o c w e l s 1 c k l c u p c 6 t i b 0 5 t i b 1 l o r t n o c w e l s 1 t k l c u p c 4 t i b 0 3 t i b 1 l o r t n o c w e l s 2 c k l c u p c 2 t i b 0 1 t i b 1 l o r t n o c w e l s 2 t k l c u p c 0 t i b 0
6 ics951403 0486b?02/23/04 vco programming constrains vco frequency ...................... 150mhz to 500mhz vco divider range ................ 8 to 519 ref divider range ................. 2 to 129 phase detector stability .......... 0.3536 to 1.4142 useful formula vco frequency = 14.31818 x vco/ref divider value phase detector stabiliy = 14.038 x (vco divider value) -0.5 note: 1. user needs to ensure step 3 & 7 is carried out. systems with wrong spread percentage and/or group to group skew relation programmed into bytes 13-16 could be unstable. step 3 & 7 assure the correct spread and skew relationship. 2. if vco, ref divider values or phase detector stability are out of range, the device may fail to function correctly. 3. follow min and max vco frequency range provided. internal pll could be unstable if vco frequency is too fast or too slow. use 14.31818mhz x vco/ref divider values to calculate the vco frequency (mhz). 4. ics recommends users, to utilize the software utility provided by ics application engineering to program the vco frequency. 5. spread percent needs to be calculated based on vco frequency, spread modulation frequency and spreadamount desired. see application note for software support. to program the vco frequency for over-clocking. 0. before trying to program our clock manually, consider using ics provided software utilities for easy programming. 1. select the frequency you want to over-clock from with the desire gear ratio (i.e. cpu:sdram:3v66:pci ratio) by writing to byte 0, or using initial hardware power up frequency. 2. write 0001, 1001 (19 h ) to byte 8 for readback of 21 bytes (byte 0-20). 3. read back byte 11-20 and copy values in these registers. 4. re-initialize the write sequence. 5. write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired vco & ref divider values. 6. write to byte 13 to 20 with the values you copy from step 3. this maintains the output spread, skew and slew rate. 7. the above procedure is only needed when changing the vco for the 1st pass. if vco frequency needed to be changed again, user only needs to write to byte 11 and 12 unless the system is to reboot.
7 ics951403 0486b?02/23/04 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters ta = 0 - 70c; supply volt age vdd = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = vdd 5 a input low current i il1 v in =0 v; inputs with no pull-up resistors -5 ua input low current i il2 v in =0 v; inputs with pull-up resistors -200 ua supply current i dd3.3op c l = full load 213 240 ma power down pd 0.07 0.6 ma input frequency fi v dd = 3.3 v; 12 14.318 16 mhz c in logic inputs 5 pf input capacitance1 c in logic inputs 5 pf c inx x1 & x2 pins 27 45 pf clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms skew 1 t cpu-sdram cpu xover to sdram 1.5v 68 250 ps skew 1 t cpu-pci cpu xover to pci 1.5v 186 250 ps skew 1 t cpu-agp cpu xover to agp 1.5v 138 500 ps 1 guaranteed by design, not 100% tested in production.
8 ics951403 0486b?02/23/04 electrical characteristics - ref t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output high volta g e v oh5 i oh = -18ma 2.4 v output low voltage v ol5 i ol = 18ma 0.4 v output high current i oh5 v oh = 2.0 v, -19 ma output low current i ol5 v ol = 0.8v 19 ma rise time t r5 v ol = 0.4 v, v oh = 2.4 v 0.85 4 ns fall time t f5 v oh = 2.4 v, v ol = 0.4 v 1.03 4 ns duty cycle d t1 1 v t = 50% 45 54 55 % jitter t jcyc-cyc5 v t = 1.5 v 521 1000 ps 1 guaranteed b y desi g n, not 100% tested in p roduction. electrical characteristics - cpu ( o p en drain ) t a = 0 - 70c; vdd=3.3v +/-5%; c l = 2pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance zo v o = v x ? output high volta g e v oh2b termination to vpull_up (external) 1 1.2 v output low volta g e v ol2b termination to vpull_up (external) 0.4 output low current i ol2b v ol = 0.3v 18 ma fall time t f2b v oh = 1.2v v ol = 0.3v 0.8 0.9 ps differential voltage_ac v dif note 2 vtpullup (external)+0 .6 ps differential voltage_dc v dif note 2 vtpullup (external)+0 .6 ps differential crossover volta g e v x true rise to compl. fall 1.37 1.5 v duty cycle d t2b v t = 50% 45 49.3 55 % skew t sk2b v t = 50% 48 200 ps jitter, cycle to cycle t jcyc-cyc 1 v t = vx 130 250 ps 1 guaranteed b y desi g n, not 100% tested in p roduction. 2 v dif specifies the minimum input differential voltages (vtr-vcp) required for switching, where vtr is the "true" input level and vcp is the "complement" input level.
9 ics951403 0486b?02/23/04 electrical characteristics - pciclk t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output high volta g e v oh 1 i oh = -11ma 2.6 v output low voltage v ol 1 i ol = 9.4ma 0.4 v output high current i oh 1 v oh = 2.0 v, -19 ma output low current i ol 1 v ol = 0.8v 19 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1.29 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1.02 2 ns duty cycle d t1 1 v t = 50% 45 51.5 55 % skew t sk1 1 v t = 50% 54 200 ps jitter t j c y c-c y c 1 v t = 1.5 v 104 250 ps 1 guaranteed b y desi g n, not 100% tested in p roduction. electrical characteristics - 24mhz,48mhz ta = 0 - 70c; vdd = 3.3 v +/-5%; cl = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -18ma 2.4 v output low voltage v ol5 i ol = 18ma 0.4 v output high current i oh5 v oh = 2.0 v -22 ma output low current i ol5 v ol = 0.8 v 16 ma rise time 1 t r5 v ol = 0.4 v, voh = 2.4 v 1.2 4 ns fall time 1 t f5 v oh = 2.4 v, vol = 0.4 v 1.3 4 ns duty cycle 1 d t5 v t = 1.5v 45 50.5 55 % jitter, cycle to cycle t jcyc_cyc2b v t = 1.5v 130 500 ps 1 guaranteed by design, not 100% tested in production.
10 ics951403 0486b?02/23/04 electrical characteristics - agp [1:0] t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output high volta g e v oh 1 i oh = -18ma 2.4 v output low voltage v ol 1 i ol = 18ma 0.4 v output high current i oh 1 v oh = 2.0 v, -19 ma output low current i ol 1 v ol = 0.8v 19 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.98 1.6 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.85 1.6 ns duty cycle d t1 1 v t = 50% 45 48.5 55 % skew t sk1 1 v t = 50% 4 250 ps jitter t j c y c-c y c 1 v t = 1.5 v 235 500 ps 1 guaranteed b y desi g n, not 100% tested in p roduction. electrical characteristics - sdram_out t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output high volta g e v oh3 i oh = -11ma 2v output low voltage v ol3 i ol = 11ma 0.4 v output high current i oh3 v oh = 2.0 v, -12 ma output low current i ol3 v ol = 0.8v 12 ma rise time t r3 3 v ol = 0.4 v, v oh = 2.4 v 0.96 1.6 ns fall time tf 3 3 v oh = 2.4 v, v ol = 0.4 v 0.75 1.6 ns duty cycle d t3 3 v t = 50% 45 49.5 55 % jitter t j c y c-c y c 3 v t = 1.5 v 235 250 ps 1 guaranteed b y desi g n, not 100% tested in p roduction.
11 ics951403 0486b?02/23/04 general i 2 c serial interface information for the ics951403 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending byte 0 through byte 20 (see note) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends byte 0 through byte 8 (default) ics clock sends byte 0 through byte x (if x (h) was written to byte 8). controller (host) will need to acknowledge each byte controller (host) will send a stop bit *see notes on the following page . controller (host) ics (slave/receiver) start bit address d2 (h) ack dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ac k byte 2 ack byte 3 ac k byte 4 ac k byte 5 ac k byte 6 ac k byte 18 ac k byte 19 ac k byte 20 ack stop bit how to write: controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte coun t ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack if 7 h has been written to b6 byte 7 ack if 12 h has been written to b6 byte18 ack if 13 h has been written to b6 byte 19 ack if 14 h has been written to b6 byte 20 ack stop bit how to read:
12 ics951403 0486b?02/23/04 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. readback will support standard smbus controller protocol. the number of bytes to readback is defined by writing to byte 8. 2. when writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. if for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. 3. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 4. the input is operating at 3.3v logic levels. 5. the data byte format is 8 bit bytes. 6. to simplify the clock generator i 2 c interface, the protocol is set to use only block-writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 7. at power-on, all registers are set to a default condition, as shown. notes: brief i 2 c registers description for ics951403 programmable system frequency generator register name byte description pwd default functionality & frequency select register 0 output frequency, hardware / i 2 c frequency select, spread spectrum & output enable control register. see individual byte description output control registers 1-6 active / inactive output control registers/latch inputs read back. see individual byte description vendor id & revision id registers 7 byte 11 bit[7:4] is ics vendor id - 1001. other bits in this register designate device revision id of this part. see individual byte description byte count read back register 8 writing to this register will configure byte count and how many byte will be read back. do not write 00 h to this byte. 08 h watchdog timer count register 9 writing to this register will configure the number of seconds for the watchdog timer to reset. 10 h watchdog control registers 10 bit [6:0] watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. 000,0000 vco control selection bit 10 bit [7] this bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. 0 vco frequency control registers 11-12 these registers control the dividers ratio into the phase detector and thus control the vco output frequency. depended on hardware/byte 0 configuration spread spectrum control registers 13-14 these registers control the spread percentage amount. depended on hardware/byte 0 configuration group skews control registers 15-16 increment or decrement the group skew amount as compared to the initial skew. see individual byte description output rise/fall time select registers 17-20 these registers will control the output rise and fall time. see individual byte description
13 ics951403 0486b?02/23/04 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
14 ics951403 0486b?02/23/04 cpu_stop# timing diagram cpu_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop# is synchronized by the ics951403 . all other clocks will continue to run while the cpuclks clocks are disabled. the cpuclks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpuclk on latency is less than 4 cpuclks and cpuclk off latency is less than 4 cpuclks. notes: 1. all timing is referenced to the internal cpuclk. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside the ics951403 . 3. all other clocks continue to run undisturbed. 4. pd# and pci_stop# are shown in a high (true) state. pciclk cpuclkt cpuclkc pd# (high) cpu_stop# internal cpuclk
15 ics951403 0486b?02/23/04 pci_stop# timing diagram pci_stop# is an asynchronous input to the ics951403 . it is used to turn off the pciclk clocks for low power operation. pci_stop# is synchronized by the ics951403 internally. pciclk clocks are stopped in a low state and started with a full high pulse width guaranteed. pciclk clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics951403 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics951403. 3. all other clocks continue to run undisturbed. 4. pd# and cpu_stop# are shown in a high (true) state. cpuclk (internal) pciclk (internal) pciclk (free-runningl) cpu_stop# pwr_dwn# pciclk (external) pci_stop#
16 ics951403 0486b?02/23/04 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. pci_stop# and cpu_stop# are considered to be don't cares during the power down operations. the ref and 48mhz clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics951403 device). 2. as shown, the outputs stop low on the next falling edge after pd# goes low. 3. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133mhz. similar operation when cpu is 100mhz. cpuclkt cpuclkc pciclk vco crystal pd#
17 ics951403 0486b?02/23/04 ordering information ics951403 y flf-t index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 48 15.75 16.00 .620 .630 10-0034 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.635 basic 0.025 basic reference doc.: jedec publication 95, mo-118 variations see variations see variations n d mm. d (inch) example: designation for tape and reel packaging lead free (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y f lf- t
18 ics951403 0486b?02/23/04 ordering information ics951403 y glf-t example: designation for tape and reel packaging lead free (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y g lf- t min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n a0808 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10-0039 n d mm. d (inch) reference doc.: jedec publication 95, mo-153 0.50 basic 0.020 basic see variations see variations see variations see variations 8.10 basic 0.319 basic 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) symbol in millimeters in inches common dimensions common dimensions index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c

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